ET1_EN=ET1_EN_0, MCR_EN=MCR_EN_0, SRTCR_EN=SRTCR_EN_0, OSCB=OSCB_0, ET1P=ET1P_0
SNVS_LP Tamper Detectors Configuration Register
| SRTCR_EN | SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. 0 (SRTCR_EN_0): SRTC rollover is disabled. 1 (SRTCR_EN_1): SRTC rollover is enabled. |
| MCR_EN | MC Rollover Enable When set, an MC Rollover event generates an LP security violation. 0 (MCR_EN_0): MC rollover is disabled. 1 (MCR_EN_1): MC rollover is enabled. |
| ET1_EN | External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation 0 (ET1_EN_0): External tamper 1 is disabled. 1 (ET1_EN_1): External tamper 1 is enabled. |
| ET1P | External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1. 0 (ET1P_0): External tamper 1 is active low. 1 (ET1P_1): External tamper 1 is active high. |
| PFD_OBSERV | System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) |
| POR_OBSERV | Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS |
| OSCB | Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted 0 (OSCB_0): Normal SRTC clock oscillator not bypassed. 1 (OSCB_1): Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. |